1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor wafer.
2. Description of the Related Art
FIG. 1 is a plan view showing a portion of a conventional semiconductor wafer. FIG. 1 shows a plurality of semiconductor chips 101 and a mirror chip 102 in the wafer. Each of the plurality of semiconductor chips 101, which are hatched in FIG. 1, is a normal semiconductor chip. The normal semiconductor chip indicates that it is an object of selection for assembly. On the other hand, the mirror chip 102 is a defective semiconductor chip by nature since the mirror chip 102 is arranged at the periphery of the wafer and since the circuits in the mirror chip 102 are not wired. In each of the plurality of semiconductor chips 101, a wiring pattern of an aluminum film is formed by etching. In the mirror chip 102, there is an aluminum film, which remains to be intact or remains not to be etched. Each of the wiring pattern of the aluminum film and the intact aluminum film in the mirror chip 102 is covered with a passivation layer.
In probing of the water, a file of data, which indicates the test result for each of the plurality of semiconductor chips 101 and the position of each of the plurality of semiconductor chips 101 and the mirror chip 102, is generated. After dicing of the wafer, mounting apparatus carries out wafer alignment. In wafer alignment, the mounting apparatus detects the mirror chip 102 by image recognition and relates the plurality of semiconductor chips 101 and the file of data using the mirror chip 102 as a benchmark of the position. Then, the mounting apparatus picks up good chips among the plurality of semiconductor chips 101 based on the file of data. The good chips are packaged to form semiconductor devices.
Japanese Laid Open Patent Application (JP-A-Heisei, 9-50945) discloses a technique to add an identification mark to the mirror chip 102 for easier detection of the mirror chip 102 by image recognition. The identification mark is added to the mirror chip 102 by patterning the aluminum film in the mirror chip 102, printing the identification mark on the mirror chip 102 or affixing a seal on the mirror chip 102.
In case of the structure shown in FIG. 1, the wiring pattern of the aluminum film is formed in each of the plurality of semiconductor chips 101. On the other hand, there is the intact aluminum film in the mirror chip 102. But, the brightness of the mirror chip 102 and each of the plurality of semiconductor chips 101 are close to each other, since each of the intact aluminum film and the wiring pattern of the aluminum film is covered with the passivation layer. Thus, it is difficult to distinguish the mirror chip 102 from each of the plurality of semiconductor chips 101 by image recognition. Therefore, the precision of wafer alignment may be poor.
In case of the technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 9-50945), the yield of the semiconductor devices may be reduced by the contamination of the plurality of semiconductor chips 101 with fragments of aluminum produced in the patterning of the aluminum film in the mirror chip 102. Moreover, a reticle for the patterning of the aluminum film in the mirror chip 102 adds more cost. Also, automated apparatus for printing the identification mark or affixing the seal adds more cost. Printing the identification mark or affixing the seal by hand may cause human error such as adding the identification mark to a wrong chip, resulting in the poor precision of wafer alignment.